CT pillars terminate the tip ends of gate structures in a semiconductor structure (or semiconductor). CT pillars provide tip to tip electrical isolation between gate structures disposed in separate active (Rx) regions of a semiconductor. In a semiconductor, Rx regions are where a plurality of active devices, such as Fin Field Effect Transistors (FinFETs), are disposed. The Rx regions are separated by isolation regions which have no active devices.
More specifically for FinFETs, these active devices include a source and drain region separated by a channel. The source, drain and channel are embedded in fins which extend longitudinally across an Rx region. The FinFETs also include gate structures which extend longitudinally perpendicular to the fins across the entire width of the Rx region.
Herein, the direction longitudinal to the fins is designated the “Y” direction and the direction perpendicular, or lateral, to the fins is designated the “X” direction. Therefore, the fins extend longitudinally in the Y direction and the gate structures extend longitudinally in the X direction.
In order to assure proper functioning of the FinFETs, the tip end of a gate structure cannot be terminated by a CT pillar at an edge of the last fin in an Rx region. Rather, the gate structure must be designed to overextend a predetermined minimum distance in the X direction beyond the Rx region, and into the isolation region, before being terminated by a CT pillar. Therefore, the minimum distance between one FinFET in one Rx Region and another FinFET in another adjacent Rx region must at least include the thickness of a CT pillar plus two minimum overextensions of gate structure beyond each Rx region. With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, it becomes increasingly desirable to reduce the thickness of such CT pillars, and therefore, reduce the minimum distance between Rx regions.
Prior art CT pillars may be formed by first lithographically patterning CT openings into a hardmask layer and then anisotropically etching a CT trench (or CT cut) into an underlying polysilicone dummy gate structure (for example, by a reactive ion etching (RIE) process). However, at about the 14 nanometer (nm) class of semiconductors and beyond, the required thickness of the CT pillar becomes too small to be reliably resolved by conventional lithographic techniques. As such, an exemplary embodiment of a lithographically patterned CT pillar will have a minimum width of about 20 nm or greater.
An alternative method of forming prior art CT pillars can include lithographically patterning CT openings into an amorphous carbon layer (ACL) of a lithographic stack, wherein the ACL is disposed above an array of polysilicon dummy gate structures (or dummy gates). Carbon spacers can then be formed on the side walls of the CT openings to reduce the width of the CT openings. The underlying dummy gates can then be RIE etched to form CT trenches in the dummy gates. The CT trenches can then be refilled with an insulator such as silicon nitride (SiN) or similar to form the CT pillars. However, the CT trenches become increasingly difficult to refill completely and uniformly at smaller semiconductor class sizes (such as 10 nm and beyond) due to their high aspect ratio (for example an aspect ratio of 10 or greater). Accordingly, the refilled CT trenches may include voids or air gaps in them that can cause electrical shorts when the polysilicone dummy gates are replaced by metal gates during a subsequent replacement metal gate (RMG) process.
Accordingly, there is a need for methods of forming CT pillars in gates that will enable reliable formation of such CT pillars with widths of less than 20 nm. Moreover there is a need for methods of forming CT pillars that are less susceptible to the resolution limitations of lithographic techniques. Additionally, there is a need for methods of forming CT pillars that do not require refilling high aspect ratio CT trenches in gate structures, and which can avoid voids and gaps in the CT pillars.